Hi r/FPGA,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

Every chip begins as an idea—but turning that idea into working silicon requires the right learning path. If you are a fresher wondering whether to begin with RTL, FPGA, Physical Design, Analog or Packaging, this visual guide connects the entire journey from specification to product. Start with clarity, choose your direction and build skills that lead to real semiconductor outcomes.

https://github.com/vsdip/VLSI-Design-Flow

​

I am from 4th yr ECE. After 1 Month, the core companies are coming to our campus. I was preparing for GATE exam but now I thought if core companies are also coming then I can sit in the placement and give a try ( previous year very worst placement for ECE core ). I talked to seniors they told approx 10 companies will come till December.

I have prepared Dgital design, analog etc and basics of other subjects, I need to practice pyqs of GATE but the problem is Projects in core companies. I know very little about verilog due to semester exams. I talked to placed seniors they told me to cover the basics of Verilog bcz they will ask in interview for basic circuit design for mux , adder etc and certain verilog syntax etc.

Are there any sources you can share which I can cover the verilog in 14 - 15 days ( basic to moderate level ). I am confused on searching youtube etc..

Hi everyone!

I've been working on OpenA64, an experimental Verilog SoC project.

Current repository includes:

• CPU RTL
• Cache hierarchy
• MMU
• NPU
• Architecture documentation
• MIT license
• Roadmap

The project targets a modern AArch64-style architecture and is intended as a learning and research project.

I'm especially looking for feedback on:

• RTL organization
• Repository layout
• Documentation
• Overall architecture

I'm not expecting anyone to review the entire codebase—I'd just appreciate suggestions on how to improve the project.

Repository:
https://github.com/hado14052015-design/OpenA64

Thanks!

We had digital circuit design as a subject last semester and learnt some basics on verilog coding. Can someone suggest a good structured course on verilog??

I am hosting a free webinar based on our ongoing AI-assisted Analog and Mixed-Signal Physical Design internship at VSD.

The goal is to show how students are using AI inside real VLSI workflows — not as a replacement for engineering, but as an assistant for understanding, debugging, documentation and faster design exploration.

The session will include student work on:

SRAM / memory design workflow
Mixed-signal design basics
AI-assisted OpenLane physical design
Magic, Sky130, LEF/LIB and GDS
DRC, LVS, STA and validation
What AI got right, where it failed, and why manual verification still matters

This is not an AI hype session. It is a practical showcase of how students are learning to use AI responsibly inside semiconductor design workflows.

Webinar: AI-Assisted Analog and Physical Design: From SRAM to Mixed-Signal GDS
Date: Sunday, 12 July
Time: 11:00 AM – 12:00 PM IST
Mode: Online
Certificate: For live attendees

Registration form:
https://forms.gle/UFjy7qzSnfQaY4JU8

This should be useful for students, faculty members, VLSI beginners and anyone curious about how AI can be used practically in analog, mixed-signal and physical design learning.

Hi! I recently took a course on SystemVerilog and really enjoyed it, so I spoke to one of my professors about potential projects. Although I’ve only worked on basic things at university—like muxes, demuxes, FSMs, and frequency dividers—I somehow came up with the idea of detecting cats (or anything else) without using machine learning. Do you have any ideas on how I could implement this? I know it might be difficult, but I’m willing to learn whatever it takes.

Hello everyone, starting of this year one of my friends recommended Neovim as a IDE for my college(Currently about to enter my Senior Year), and I absolutely fell in love with it, while using C and C++. But my work also requires Verilog System Verilog and UVM. And I tried enough with AI to get my vimrc and lazyvim to match C and C++ standards. So the question is are there any V/SV plugins that match what C and C++ plugins do. Note that I tried svlangserver and verible and found that it does'nt even recognize some SV words like mailbox etc. So what's the way out. :wq (Posted on Both Vim and Neovim communities).(I also have severe skill issue in VS code so)(I use vim at work so I am comfortable at both)

A lot of students want to enter semiconductor design, but many get confused about where to start.

Some jump directly into physical design.
Some start with RTL.
Some try analog first.
Some only watch videos and collect certificates.

In my opinion, a beginner-friendly roadmap should look something like this:

1. CMOS Understand transistors, basic circuits, SPICE simulation, and how devices behave.
2. RTL Learn Verilog, digital logic design, testbenches, and simulation.
3. Physical Design Understand synthesis, floorplanning, placement, CTS, routing, timing, and how RTL becomes layout.
4. Physical Verification Learn DRC, LVS, antenna checks, density, PEX, and what it means to make a design tapeout-ready.

For someone who already knows RTL and basic physical design, jumping directly into an internship-style physical design project may make more sense than restarting from zero.

The bigger point is this:

Interest in semiconductors is not enough anymore. Students need proof — GitHub work, simulation results, reports, screenshots, debug notes, and projects they can explain.

Curious to hear from people already working in VLSI / semiconductors:

Would you change this order?
Should beginners start with CMOS first, or RTL first?
What would you tell a student who wants to enter chip design seriously in 2026?

I recently designed and documented a 4-bit multi-cycle CPU in Verilog HDL as a personal learning project. This comes after I completed the standard Digital System Design (DSD) course of my college.

I tried to document in a technical report format, explaining the ISA, specs, architecture, design decisions and debugging experience.

I would really appreciate technical feedback from people with more experience, any issue with the structure, design or anything else that could help me improve future projects.

GitHub repo: https://github.com/theYash856/4_bit_Multi_Cycle_CPU

Any constructive criticism is more than welcome.

A live demo video is worth more than 100 AI-generated project posters.

Maaz Mahmood joined the VSD RISC-V FPGA IP Internship as someone completely new to FPGA and RTL design.

And now, in this video, he is confidently demonstrating his own SPI Master IP running on real FPGA hardware.

He built the IP from scratch, integrated it as a memory-mapped peripheral inside a RISC-V SoC, flashed it on the VSDSquadron FPGA Mini board, and validated the transmit/receive path using hardware loopback.

This is what I like most about his demo:

No fancy editing.
No buzzwords.
No “project idea” slide.

Just a student, his FPGA board, his terminal output, and proof that his IP is actually working.

Great work, Maaz. This is exactly the kind of confidence students need before entering the semiconductor industry.

I used to use chipdev.io site to learn verilog. But the site is now shutdown.

Does anybody have the questions downloaded from chipdev.io ?

Also, could you please share good resources for verilog rtl design (Microarchitect) Interview preparation....?

#verilog #rtl #microarchitecture #interview #chipdevio

Indie engineer here. Got tired of writing testbenches by hand and built this: https://testbench.co.in

Paste a Verilog module → complete self-checking testbench, runs with iverilog. No login, free.

The prompt is grounded in actual verification literature (Cummings 2000/2003 papers, IEEE 1800, Spear's testbench book) — every timing rule it follows has a citation.

I tested across 7 design classes (counters, FSMs, FIFOs, shift registers, pipelined multipliers, LFSRs) — works well on most, struggles with LFSRs and Mealy detection cycles (honest limitation, documented).

Would love feedback — what designs would you throw at it? What's missing?

[[email protected]](mailto:[email protected])

Learning verilog bymyself and was intrested in how SPI CPHA and CPOL work so I decided to ask AI mainly deepseek, what do you guys think, why does it seem to be giving wrong answers ?
https://chat.deepseek.com/share/3jsfsmx7s7zujtma3z

Hi i am actually building and RTL coding platform for 2nd and 3rd year ECE/CSE students.

Before that my intro I am 2025 batch passed out from ECE tier 3 clg like other my clg placement sucks... But ya I was truly committed towards the VLSI I did lot of self study and did few of there kinda RTL projects but ya as I dint had the trained certificate from good institutions I was getting rejected from most of the companies that I apply and I have done 2 interships in RTL role , also have one tapeout also. But ya the process of self learning is truly something unstructured and most of the colleges introduce the subject of VLSI at 3rd or 4th yr and students get the exposure towards it at very end of there engineering. So i want to build this platform for them more focused towards 2nd and 3rd year students where they learn digital electronics, RTL design (verilog, system verilog) , and how does this RTL codes actually map to the real hardwares how that code will actually work in real silicon that is where students understanding the concepts in depth. So as I am not yet industrial person with experience I want some experienced or a Knowledge person who can guide me to build the curriculum for those students who wanna do self learning but in a proper manner that industry wants from a fresher. So if even a single contribution from most of you guys would literally help me to build a proper worthy platform for most of students becz most of them are passionate but cant afford the fees and if they are exposed to this domain at earliest with proper structure then we can contribute growth of semiconductor industry with quality workers.... Please DM me i really need help.

Hi everyone.

I’ve been working on an experimental GPU architecture written in Verilog/SystemVerilog, currently targeting FPGA simulation and partial FPGA validation on Artix-7 hardware.

The project is called NovaGPU TS1T, and the main research focus is a token-driven execution model called N.E.O.N. (Neural Execution and Operand Network), which tries to reduce some traditional scheduling/control overhead by using dependency-driven execution inside parts of the graphics pipeline.

Current work includes:

Tile-based rasterization

Fixed-point graphics pipeline

Experimental token matching unit (TMU)

Deterministic tile arbiter

Basic BVH traversal experiments

SRAM bridge/cache experiments

FPGA-oriented pipeline partitioning

Important clarification: This is not a “finished GPU” or an NVIDIA competitor. The current implementation is mainly:

RTL research

architecture experimentation

simulation validation

FPGA feasibility exploration

The FPGA target is currently an Artix-7 platform, with reduced-scale functional models for memory and compute resources.

Some things I’m actively working on:

critical path reduction

timing closure

BRAM/DSP optimization

valid/ready synchronization issues

pipeline staging

TMU occupancy handling

I recently updated the documentation/whitepaper to better reflect realistic FPGA constraints and implementation limitations.

I’d genuinely appreciate feedback from FPGA and graphics architecture people, especially regarding:

timing strategy

token/dataflow execution practicality

FPGA scaling concerns

verification methodology

memory architecture tradeoffs

Project: https://github.com/nova-studios-hw/novagpu-ts1t

Whitepaper + architecture docs are included in the repository.

Thanks.

I have used RTL files for few digital blocks while running mixed mode simulation in CC Synopsys. how to probe internal nets or wires of verilog?

Hello. I am new to learning Verilog, where I have some background in VHDL. Can anyone give me some good resources for beginners to learn the syntax, best practices, etc? Thanks!

Hello people from r/Verilog!

I’m conducting a research at the Federal University of Alagoas (UFAL), Brazil. The goal of this study is to better understand how the community interprets and reason about SystemVerilog (HDL) code practices.

Whether you are an experienced HDL developer or still building your experience, your perspective is valuable.

Survey link (Google Forms):
https://forms.gle/RGC6A5JNMd5xjjCM8

Estimated Time: 5 – 10 minutes

Disclaimer: This survey's purpose is not to train or obtain any information for any AI training or such, it is entirely anonymous and will be used exclusively for academic and educational research purposes.

Thank you for your time!