I just completed a "basic" verilog/system Verilog course that focused on the basic building blocks (gates, MUXs, registers, counters, CPU, etc). I've only worked with Intel / Quartus ecosystem. I understand the difference between structural and behavioral models (and it seems like the RTL is roughly similar for both, assuming your structural model uses optimal logic blocks) I'm looking to "level-up" my FPGA programming skill by working on more complicated logic.

FPGA Engineer here. 10 years experience. Have worked end to end from
RTL to hardware testing and shipping products in Intel/Altera FPGAs.

* Decent RTL design knowledge
* Sanity Simulation
* Quartus Flow
* Python for Hardware Testing
* board bring up and hardware testing, integration with other HW modules.
* communication protocols: Ethernet, RS232, Aurora, JESD, I2C

Sometimes I do feel my VHDL/verilog understanding is not enough.
I do feel I haven’t worked on timing analysis enough.

Want to explore:
DSP/ signal processing
HFT

Career advice? Or any guidance for me?

Thanks for your time

I believe that AI can do this conversion to some extent. Are there any tools which do this job?

Hi all.

I'm a fairly experienced electronic engineer with a good 12 years in RnD for new products (STM32/ESP32 mostly)

At our company I'm one of 2 electronic engineers, the other guy I do not think has much FPGA experience.

Our company has a new project on the horizon that will scan an object and get point cloud data and stream to a PC.

(I'm being intentionally vague due to the project and company dynamics - sorry)

The idea is to then build up a 3D scan of this object on the PC.

This has been prototyped by another company so it is proved to work but it would be up to us to make everything fit in the required housing and finish off the product.

I know that is easier said than done but it always is.

I'm hoping someone can help me with some idea of what I'd get into it I put my hand up for this project.

I'm interested in getting some FPGA experience in both the hardware and programming side of things but if this project is going to be too much for me then the boss has mentioned hiring a FPGA engineer specifically.

The problem I see with that is that there is little else after this project for that skill set and it's another drain on the (to be frank) dwindling companies resources.

I did some CPLD projects back in Uni days but that is the extent of my experience and I know it would be basically learning it all again.

Does anyone have any idea what I'm getting myself into with this or could point me to some starter resources to help better understand what type of can of worms I'm opening.

I don't have time right now to do dev work as the current work load is a lot but after I've gotten the 3 projects finished up in about 6 months from now I'd look at starting this.

Any advice would be helpful.

Hi there,

I announce that I've started to work on try to provide a open source toolchain for this FPGA, which was released in 2009 and is cheap and capable.

It can run some soft core like neorv32 and it can be found relatively cheap on aliexpress.

I don't know if someone else if working in the same, at least by a initial search I not found anything.

The goal is to integrate with yosys and nextpnr and be able to use like others FPGA such as ICE40 series.

The current status is that I'm able to generate valid modified bitstreams and now I'm digging in the most complex part: the routing network. So it's more or less on track.

There is a long road ahead, I don't if I will have the time to complete it. Any help like a project start is appreciated!

Repo: https://gitlab.com/franlego98/siroco Docs: http://siroco.franlego98.dev/

See you!

PD: name comes from a wind typical from the Iberian peninsula, there is a project called mistral that is a wind of France, so all names are related to wind phenomenons, Cyclone, Mistral, Siroco...

A client is investigating porting an existing design from Xilinx 7 series to Altera Agilex 5. It's an almost 100% portable RTL design, so no problems there.
I am having timing convergence issues though, which I didn't expect because the 10nm Agilex 5 (even in the slowest, lowest power "B" group) ought to be much faster than the old 28nm Kintex 7 part (which easily met its timing goals without needing the fastest speed grade).

Further investigation revealed that most of the Agilex 5 fabric is indeed faster (actually it's pretty nice), however the M20K RAMs, when used in modes (e.g. TDP) that have two read ports, are much slower than the equivalent RAMB18.
This design has a lot of those, unfortunately.

I have come to the conclusion that the M20K is in fact not a dual port RAM and is somehow multiplexed between the two ports (e.g. it's double pumped like Xilinx's URAM). It also doesn't natively support a clock domain crossing TDP mode and if you try to synthesise one of those (e.g. via an altsyncram instantiation), it will add a CDC FIFO to move the I/O from one clock domain to the other, with some restrictions on the clock frequency ratio. Yay.

My question: Does anyone actually know how single clock DP RAMs are implemented with the Agilex M20K? Is it a double pumped single port RAM (which would explain the slowness wrt the natively dual port RAMB18)?

The FAE didn't have any suggestions.

EDIT: I can get the Agilex 5 design to meet its timing goals if I use a faster part (in the "A" group), but that costs significantly more than the Xilinx part it's replacing.

That is all.

Is it possible access data directly from the APU's L2 cache and send it to the host system via PCIe?

For a heterogeneous deployment, squeezing an entire video-and-action model onto an FPGA seems like the wrong starting point. Assume the causal transformer and sparse expert routing stay on a GPU. Is there still a useful deterministic block to move next to the sensors?

LingBot-VA 2.0 combines a semantic visual/action tokenizer, a causal DiT, and sparse expert layers. A first candidate is the fixed-shape preprocessing and tokenizer front end, provided the activation transfer does not erase the latency gain. A second possibility is a heavily used matrix kernel with stable dimensions. The irregular expert routing can stay on the host.

Before choosing a board, the first pass is to trace tensor shapes, external-memory traffic, precision sensitivity, and worst-case latency over a control sequence. For a hard control deadline, the slow tail matters much more than average utilization. The stop path would stay on an independent controller either way.

For people who have profiled a similar FPGA plus GPU split, which measurement showed early that the partition was worthwhile, or that PCIe and memory traffic had already killed it?

I'm writing a thesis and going through sheet paper "FPGA Architecture: Principles and Progression" by Andrew Boutros and Vaughn Betz.
There is a diagram showing how Xilinx and Altera differ in using fracturable LUTs in calculating full-adder logic.

Xilinx is using a pair of wires and added MUX with selector pin connected to 'prop' output of top 4-MUX.

I have a problem to see the entire picture though and was unable to find any better diagram or explanation.
It is confusing that what exact function does each 4-MUX use and what is 'gen' selector being controlled by.

According to Xiling fracturable 6-LUT diagram, 'gen' MUX is being selected by 4-th pin, which is not anyhow related to full-added logic at all (full-adder should use only 3 input pins).
Do authors imply that 'gen' MUX selector value is irrelevant?

Bottom 4-LUTs probably are easy to guess as depending on C_out[i-1] value bottmo MUX should output either XOR(A,B) or NOT XOR(A,B). But still not 100% sure.

Could anyone help to understand how it works?

Hi r/FPGA,

I’m building OpenCoreLabsX, an open-source collection of reusable SystemVerilog IP cores for FPGA, ASIC, MCU, SoC, and RISC-V projects.

Current cores include APB I2C, APB Timer/PWM, APB USART, and an AXI QSPI controller.

We are looking for contributors interested in:

- Designing a new APB GPIO controller

- Building an I2C slave BFM and corner-case regression

- Adding Timer/PWM assertions and boundary tests

- Implementing a USART serial monitor and error injection

- Building a QSPI flash model and end-to-end XIP verification

Contributions can be small and focused. You can work on RTL, UVM, assertions, functional coverage, documentation, or technical review.

Beginner-friendly tasks are available, and each issue includes its scope, deliverables, and acceptance criteria.

Contributor task board:

https://github.com/OpenCoreLabsX/.github/issues/2

Organization:

https://github.com/OpenCoreLabsX

Technical feedback is also welcome. Thank you!

I'm running into an issue with the AMD AMR platform on an Alveo V80 and was wondering if anyone has seen something similar.

I'm using the stock AMR image (no custom RTL), and the card boots normally after a cold power cycle. However, whenever I execute:

sudo ami_tool device_boot -d <BDF> -p 0

the entire host becomes unresponsive and requires a cold reboot. A normal reboot is not enough to recover the card.

Some additional observations:

• ami_tool cfgmem_program -q works without any issues.
• Reflashing the card over JTAG multiple times doesn't change the behavior.
• When using JTAG, I have to disable the PCIe slot in the BIOS, otherwise programming fails.
• The same server previously ran AVED without any issues programming PDIs.

After rebooting, the QDMA driver consistently fails to initialize with messages like:

hw_monitor_reg: Reg read=399 Expected=0, err:-3
eqdma_cpm5_indirect_reg_clear: hw_monitor_reg failed with err:-3
qdma_device_init: init ctxt write failed
probe of 0000:d8:00.1 failed with error -16

I'm not sure whether this is the cause of the crash or just a consequence of the device reset.

I've opened a GitHub issue with more details here:

https://github.com/Xilinx/amr/issues/8

If anyone has experience with AMR on the V80, runtime device_boot, or similar CPM5/QDMA issues, I'd really appreciate any suggestions or pointers.

Simulators are great for perception, but they completely miss the hardware-execution gap. How are you guys profiling power transients (dI/dt) and thermal throttling under real electrical loads? I'm building a local CLI to orchestrate this on custom PCBs because Isaac Sim doesn't catch melted silicon. Are you all just writing custom Bash scripts to poll JTAG

Hi Everyone,

When i create a platform using the XSA of a previously synthesized vivado hardware config and try to create an Application component in it i get "Your platform repository does not have any platforms compatible with app_component". I have tried : making new platform, new workspace, new xsa and nothing seems to help. did anyone else ever experience this issue?

I am using vivado 2026.1

Any help would be much appreciated!

-Jan

I see a bunch of Alveo U25 boards listed on eBay for decent prices (~$350 USD).
I know people recommend the U50 or higher($$$) but I want to know if it’s possible to get the U25 to work for general programming considering it’s one of the few Virtex tier FPGAs that can work with the free Vivado license.

Anybody here use the U25 for personal projects?

This is crazy, but you never know until you ask. So…

Does anyone have an spare FPGA that they aren’t using, but that it still works, that would be willing to gift it for free???

I know I am probably asking for too much. But, I am asking because I recently worked with an FPGA for a university project and I loved it. But, upon checking them out online, I’ve realize that they are too expensive for my budget.

I would love to build projects and get a bit more experience that way! You know. For employers!

In case you are curious, I worked on a intel FPGA using what I believe was SystemVerilog.

Thank you for your time, and reading my post!!

Releasing Ostomachion v1.0.0, an open-source FPGA platform I have been developing. It integrates a soft RISC-V core, a real-time operating system, and a signal-processing accelerator so that each layer is a thin, well-defined interface over the one below. It runs on an Artix-7 (Opal Kelly XEM7310):

- A NEORV32 RISC-V soft core running the Zephyr RTOS, bare-metal on the fabric.

- A streaming frequency-domain datapath in hardware: a 4096-point FFT, a per-bin programmable complex filter (a coefficient mask H[k] in block RAM), and an inverse FFT — staged through AXI DMA and BRAM, with interrupt aggregation onto the core.

- A header-only C++20 hardware abstraction layer that presents the accelerator to software as ordinary typed calls, so the path from a std::span in a unit test down to a beat on an AXI-Stream bus is a sequence of deliberate, inspectable wrappers.

The whole Vivado block design regenerates from a version-controlled Tcl script — no saved checkpoints, no hand-edited GUI state. Every bitstream derives from text alone, which makes the hardware auditable and diffable in the same way as the software.

The name is Archimedes' Ostomachion, a dissection puzzle of fourteen pieces; the platform is likewise fourteen composable layers, each replaceable in isolation.

A companion desktop application drives the full filter datapath on live hardware over USB: it streams frames to the fabric, programs the filter mask in real time, and plots the input, the mask H[k], and the filtered output as the transform runs — the genuine hardware pipeline end to end, not a software model of it.

Source, documentation, and design rationale (GPL-3.0; commercial licensing available):

github.com/andynicholson/Ostomachion

Hey everyone,

I wanted to share a capstone project I recently wrapped up and pushed to GitHub: a heterogeneous System-on-Chip (SoC) deployed on a Nexys A7 FPGA.

The main goal was to bridge high-level computer vision software (Python/OpenCV) with raw silicon using a custom hardware-software co-design.

Key Features of the Architecture:

• Custom RV32I Single-Cycle Core: Acts as the central firmware orchestrator, executing custom RISC-V assembly.
• Parallel MAC Accelerator: A custom 3x3 convolution block featuring 9 parallel multipliers and a log-depth adder tree to compute spatial derivatives (like Sobel-X) in a single cycle.
• Native CV_8U Hardware Clamping: Built-in combinatorial absolute value and saturation logic that matches OpenCV's clamping behavior (CV_8U) directly in silicon, avoiding two's complement wrap-around artifacts.
• MMIO Interconnect: Uses a 32-bit Memory-Mapped I/O bus to route data between Data RAM, the UART peripheral, and the accelerator.

The Hardest Engineering Hurdles & Fixes:

1. Setup Timing Violations: Early iterations used a linear accumulation chain for the 9 multipliers, which completely wrecked the critical path. I restructured the datapath into a log-depth parallel adder tree to resolve setup slack and hit a clean Setup WNS of 0.51 ns at 50 MHz.
2. UART Buffer Overruns / Smearing: Blasting 9-byte windows from Python over serial caused the FPGA receiver to drop bytes and scramble pixel arrays. Fixed it at the link layer by implementing a paced Big-Endian serial transmission protocol with rigid 2ms delays between bytes.

The repository includes the complete RTL (/rtl), host-side Python test/debug scripts (/sw), and a full architectural breakdown.

GitHub Repo: https://github.com/waseemnabi08/rv32i-vision-soc

I'd love to hear your thoughts, feedback, or any questions about the microarchitecture or verification process!