Hi — I’m building a digital effects pedal on a Teensy 3.6 and I’d like a sanity check on the analog input preamp before I wire it on a breadboard.

Goal

• Guitar / phone / mic jack → preamp → Teensy A2 (ADC)
• Single supply from Teensy VIN (~5 V)
• Hardware gain pot + later software gain in firmware
• Keep the ADC input roughly in a safe range (ideally centered for 0–3.3 V reading after coupling/divider)

What I simulated (EveryCircuit)
Ideal op-amps with Min = 0 V / Max = 5 V to mimic single-supply rails (stand-in for LM324 sections).

1. Bias: VIN → 10k → mid (~2.5 V) → 10k → GND, with 10 µF to GND
2. Stage 1 (non-inverting gain):
   • Input: AC couple 10 µF → 10k into +
   • Bias: 100k from mid-rail to +
   • Feedback: 100k pot (both ends to OUT, wiper to −), 2.2k from − to mid-rail
3. Stage 2 (buffer): AC couple 10 µF into +, 100k from mid-rail to +, − tied to OUT
4. To ADC: AC couple 10 µF → 10k series → node “A2”, 10k to GND

Test source: ~100 mVpk, 1 kHz. With the pot mid/high I get a clean sine on the A2 node (AC around ~0 V after the last coupling cap / divider).

Questions for review

1. Is this a reasonable LM324 single-supply preamp for line/instrument levels into a Teensy ADC?
2. Anything you’d change for stability/noise (biasing the buffer input, C values, pot wiring as rheostat vs both-ends-to-OUT)?
3. After CO + 10k/10k to GND, DC at A2 sits near 0 V and the signal is bipolar in the sim — for a real Teensy A2 pin, should I instead bias that node to ~1.65 V (e.g. divider from 3.3 V), or is AC-coupled into a ground-referenced divider acceptable if amplitude stays small/positive enough?
4. Any red flags before breadboarding (input protection, RF, power decoupling, headroom with LM324)?

Happy to adjust values or simplify the second stage if that’s overkill. Thanks!

This is small project I have been working on.I intend to make it into a PCB. How is it? Should I make any changes?

Hi everyone,

I’ve been doing some market research looking for a reliable netlist-to-schematic converter that outputs clean, human-readable diagrams (especially given how often LLMs and scripts spit out raw netlists or ugly grid stubs). Aside from basic layout engines or specialized SPICE tools, I haven't found a robust, modern solution.

Because of this gap, I'm considering building one myself.

Before diving too deep into development, I wanted to run a few questions by this community:

• Target Formats: Which schematic tool outputs/formats are most commonly used in your workflows today? (e.g., KiCad .sch/.kicad_sch, Altium, LTspice .asc, etc.)
• Product Model: Assuming a tool like this existed as a cloud/SaaS product, would you or your team be interested in using it as a paid service?
• Must-Have Features: If you were paying for a tool like this, what features would be non-negotiable? (e.g., round-trip connectivity verification, custom symbol mapping, hierarchical block structuring, automated layout arrangement)

I'd love to hear your thoughts, whether you'd find this useful, or what hidden gotchas I should watch out for when trying to map topology back into a readable diagram.