I’m preparing for design interview and saw a synchronous FIFO coding problem and want a sanity check on the full-boundary behavior.

(original problem: ASIC.FYI Q892⁠ )

My implementation is:

assign rd_valid = !empty;

wire pop = rd_valid && rd_ready;

assign wr_ready = !full || pop;

wire push = wr_valid && wr_ready;

——
If the FIFO is full and a read is accepted, this also allows a new write on the same edge. Occupancy stays full and there’s no bubble.

The downside is that wr_ready now has a combinational dependency on downstream rd_ready. The simpler alternative is probably assign wr_ready = !full;

That removes the path, but the replacement write isn’t accepted until the following cycle.

If a spec only says “implement a synchronous ready/valid FIFO,” which behavior would you normally assume? Is the full-boundary exchange part of expected FIFO behavior, or just a throughput optimization that needs to be stated explicitly?

This is my very first iteration of VCO layout (first time CMOS layout as a total beginner), I haven't even ran a DRC yet but I just want to share! I love analog and chip design!

Hi guys.. has anyone worked on PHY layer as firmware side for SERDES protocols? Have interview lined up tomorrow I want to know what to expect in general topics wise? Thanks

Hi,

Is there anybody who did a RISCV verification course from maven silicon in the past or similar course related to verification, do they reach well ? Will they be providing actual RTL and explain verification or just a high level system verilog model which is not what companies do

Can someone explain the process of tape-out and why it is such a valuable experience for a research student? I don't have the finances/opportunities to send my chip for tape-out since i am working on some other research topic in digital in my uni, but can I do everything on my own before sending it, since after tape-out it's binary — either working or not — so there isn't really much to learn from the outcome itself?

As title says, I submitted on July 7th and I can't stop thinking about it.

Let's start with the fact that this tapeout is my master thesis project and it was my very first approach to ic design, microelectronics in general (I had general knowledge, but never had dedicated courses)

I liked it a lot, but it was one of the most stressful things I've done my whole life. And the worst thing is that I am realizing that I may have underestimated some stuff only now, after submission (the circuit goes at cryo, so some stuff has to be implemented knowing that the result may be different from simulations)

I had seven months to design the chip and now that it's submitted I have continuous thoughts about how I could have done better/realization for minor fuckups that may be fixable.

So my question is: is it common to make stupid mistakes? Or better, how do you cope with it?

I always hear about people in the lab doing silly mistakes, but now it may happen to me the whole world feels like it's crumbling under my feet. What stresses me out the most is that I feel like the impression of myself I left on my supervisors is getting destroyed at every mistake I tell them (now that I left it's even worse since I can't even talk to thema face to face)

Everyone here has debugged a reset-release metastability at 2am, and everyone knows the testbench never sees it. We built an open evaluation layer that adds declared intent (clock groups, reset discipline, power-on state) plus a structural oracle on top of the functional result, and ran frozen generation studies against it.

The finding practitioners will recognize: at least 14 of 57 functionally accepted candidates wire raw async reset into operational state, and every single one also contains a correct two-flop synchronizer in the same file, with its output used as a synchronous qualifier while the async pin stays raw. A junior who does not know the idiom omits the synchronizer, which review catches. These candidates build it and route around it, which defeats exactly the heuristic reviewers use.

One public example even carries the comment "Synchronized active-low reset applied directly to counter state" above the wrong wiring.

An independent RTL engineer reviewed the frozen packet blind this weekend and concurred on every case he examined, including calling the synchronizer bypass unprompted. Artifacts, prompts, and both oracles are public; `svgap demo` reproduces the witness split in one container command. For FPGA folks: yes, sync-reset methodologies change the flavor; the intent declaration question stays.

Curious what this crowd thinks belongs in a task-level intent contract: which production question does a functional pass leave unanswered in your flow?

  Repo and artifacts: https://github.com/shsridhar-beep/svgap

Hi all, I work as an Analog Layout Design Engineer at one of the top VLSI companies with ~2yoe. Ik I'm in the very early stages of my career, and I genuinely feel I'm good at my job and enjoy what I do. I was wondering if I could get converted to an FTE from being a temp employee and what the odds are. How long does it usually take? How often does it happen? Am I even being realistic to expect an FTE offer?

I'd like to hear your stories if you've gotten an FTE offer from your client company or if youve come across someone who has gone through this

I am using Innovus (with Stylus) 23.11 to implement a simple block (180 nm node, 300x300 um, 1200 instances, 100 MHz clock). I was handed some scripts for Innovus that were used to implement previous designs. However as they were something of a mess (for starters, there was no proper CTS), I based my flow on the Innovus' built-in "block" flow template.

1. Is it possible to avoid DRC spacing errors due to CTS nets? These occur because CTS nets on M2 go too close to standard cells' M1 pins to which M2+ signals have to be connected somehow to route them elsewhere.

2. In the "block" flow template where are we supposed to put power routing? For now I just pasted commands from our previous scripts to the init_floorplan step

3. Is it possible to re-route wire fragments quickly as in Virtuoso? In Virtuoso I use "P" tool which allows for quick bypasses - if I route from and to the same wire, then it deletes that old section and substitutes it with what I have drawn. Also, not sure how to quickly switch layers with inserting a via (when I am going in only one direction e.g. vertical).

4. How to automatically insert pin shapes (Metal n, purpose pin) so that when I import GDS to Virtuoso it will recognize connectivity and allow for auto-routing? By default it just puts a label (Metal n, purpose text) where the pin is

I have unvested stocks vesting Aug 9 and September 15. It's been hell with my manager navigating the informal pip. Which option should I take and would either option let me access the unvested stocks ?

I designed a high-performance INT8/BF16 MAC using the OpenLane ASIC flow and the Sky130 HS standard cell library.After my LinkedIn post, I further optimized the performance of both the BF16 and INT8 MAC units. As a result, some of the reported metrics differ slightly from those in the LinkedIn post, but the overall results remain largely the same.

repo: https://github.com/wer-eng/sky130_high_performance_mac/

linkedin: https://www.linkedin.com/posts/ey%C3%BCp-sa%C4%9Fd%C4%B1%C5%9F-246490218_asic-vlsi-opensourcesilicon-ugcPost-7484691343953367040-Bjrb/?utm_source=share&utm_medium=member_desktop&rcm=ACoAADbjSlYBzeykhKHE0CvwieNA-6JUQVzgvcQ

Hi everyone,

I have a written test coming up for an Analog Layout role at SiTime Semiconductor, and I'd like to prepare as effectively as possible.

Could anyone who has gone through the process share:

What topics were covered in the written test?

Was it mainly analog layout, analog circuits, MOSFETs, semiconductor basics, or aptitude?

Were there any layout-specific questions (matching, common-centroid, DRC/LVS, LDE, etc.)?

Any suggestions on what I should focus on before the test?

I'd really appreciate any insights. Thanks!

Hi Guys,

I am having a in-person interview at Graphcore as silicon Design engineer. Anyone have any experience attending the same.. can you tell me what to be prepared off

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Hi everyone,

I'm from India and I've recently started looking into doing my Master's in Taiwan. I'm interested in VLSI/IC Design, especially ASIC Physical Design, because I want to build my career in the semiconductor industry.

The thing is, I'm still at the very beginning of my research. I haven't decided on a university or even a specific program yet, so I'm trying to learn as much as I can before making any decisions.

If you've studied in Taiwan (or are currently studying there), I'd really appreciate your honest opinion.

A few things I'm curious about:

- Which universities are actually worth considering for VLSI or semiconductor-related programs?

- How's the overall student life and workload?

- Are scholarships common for international students?

- Is it possible to get internships during the Master's?

- How difficult is it for international students to get jobs after graduation, especially at companies like TSMC, MediaTek, UMC, Realtek, NVIDIA, Qualcomm, Synopsys, or Cadence?

- How important is Mandarin for daily life and for getting a job?

- Looking back, was studying in Taiwan worth it?

I'm also interested in hearing about things that aren't usually mentioned on university websites—the good, the bad, and the unexpected. If there was something you wish you'd known before moving to Taiwan, I'd love to hear it.

Any advice, personal experiences, or recommendations would mean a lot. Thanks!

Hello nice people of Reddit,

For the past 7 months, as part of my PhD, I have been working on a Verilog simulator, and since the paper just got accepted, I can finally share it.

Verilog is the language used to describe hardware designs, especially heavily as you get closer to the final gate-level netlists. Vogls takes these designs and simulates them according to the Verilog 2005 scheduling semantics.

Repository: https://codeberg.org/coastalwhite/vogls Preprint: https://arxiv.org/abs/2607.15782

We use this simulator to do pre-silicon side-channel analysis, which typically involves capturing a bunch of signal traces around a short point-of-interest. There was no simulator that allowed full-timing simulation and was versatile enough to do what we wanted, so we built our own. It is currently still very much alpha software, but we use it to do research, and it can simulate many designs such as masked AES cores, RISC-V processors, and floating-point accelerators.

A few things that it has: - A bytecode and compiled backend - A Python library that you declaratively describe side-channel analysis plans in - Standard Delay Format (SDF) and specify block support.

To prove to myself it can be used as a library in tools, I also created Pipeline Explorer which uses Vogls under the hood to simulate and inspect the pipeline cycle-by-cycle for several RISC-V CPUs.

There is still much to do, but I am thrilled to share this now.

AI disclosure (because people will ask): I did not use any AI for the main codebase except for the equivalent of googling. I did use AI for three main things: 1. Debug large Verilog designs that did something wrong and reduce to MREs. 2. Prototype Pipeline Explorer, but after the performance of the UI was horrible, I rewrote most of it by hand in vanilla JS and canvas. 3. The temporary testing infrastructure for the small RISC-V assembler I wrote is also AI. I will likely remove this at some point because it is unreadable.

Like in software there are usually bugs and fixing is easy but in hardware any bug is either millions of dollars to fix or impossible.

By big I mean that on some path of the chip there was supposed to be a high signal but it was interpreted as a low signal.

Because I didn't learn it yet but I heard modern chip have error correction hardware baked in so I wonder if such bugs even exist in hardware at all.

(Not including cosmic rays that flip bits and these crazy things, normal operating on earth)

I recently graduated from one of the best universities in Pakistan. I wanted to land a design role but was unable to do so and since the industry here is quite young and there are a couple of startups that were hiring, I ended up working as a verification engineer at a startup in my university. We have a small talented team that works mainly on accelerating Cryptography.

So far it has been a 3 weeks and I'm in the process of rehashing UVM. I like the job although all I have done is training, I will reserve my judgements till the actual work stress dials in lol.

I know it is too early to say this but to the veterans of this industry do you have any tips on what I should get used to early on? What methodologies I can use to better verify design and most importantly how can I automate my work? I really love efficiency and would love to integrate little things here and there to better the way I work and the others around me work. What advice do you have for me for this role? What should I focus on amd look out for? How much growth is in this career?

Another set of questions comes from career perspective. I'd one day like to lead teams to tape a product out, quite possibly start my own start up. How does a verification engineer fare as a career in this regard. I mentioned earlier that i was chasing after a design role and although I am really grateful for my job, I'd love to do design cuz problem solving. How difficult is it to switch roles let's say 3-5 years down the line? I consider every moment of life as an opportunity to grow, improve and learn. So switching roles, building the one or two odd project on the side, going for more education and further learning are always welcome and a part of life so I am willing to do a number of things. How can I make the most out of this career. Also any dos and don'ts

Thanks in advanvce for all the advice and suggestions. I really appreciate it.

I also apologise in advance if this seems a bit too much or my questions are a bit rushed given where I stand, I am looking for advice and suggestions as the industry here is not large enough to give me a proper outlook on the bigger scheme of things. I like the ndustry so I'd most likely have to relocate to another country for better opportunities eventually. The earlier I understand what my choices are, the better. Thanks

i recently got into asic design (im a beginner, having done just one asic project using open source tools). I dont understand the fixes for STA. Usually its supposed to be performed at various places during the asic design flow, but I have a question. Lets say I finish synthesis of the RTL code, and I perform STA to find that the slack is negative, meaning there is a timing violation. Should I stop at that place, and analyse how to correct it? What are the ways by which it is fixed, the generic fixes.
But another thing I noticed was that when I ignored this negative slack and let openROAD do the placement of the asic, the timing violation was fixed by itself during this process. So should i be moving ahead as if all is well and good?